Programming a CPU is a well-known process. Even programming GPUs became easier with Nvidia’s CUDA and OpenCL. But programming a field programmable gate array (FPGA) has always been thought of as a task for chip designers, not programmers. Xilinx’s Vitis tool chain and Intel’s OneAPI are trying to change that perception. The news that Xilinx has open-sourced the Vitis HLS (high-level synthesis) front-end is another push to democratize software development for FPGAs.
It is important because some problems are best served by FPGAs with its programmable data structures and low latency throughput. FPGAs are the original software-defined hardware platform. And FPGAs allow redefining hardware functions in deployed hardware. Moving FPGA programming design to high-level languages like C and C++ opens new options for systems designers.
Open sourcing software that was previously proprietary is a great way to expand community engagement and encourage more innovation. Xilinx posted the code on the GitHub repository opening the code for the community to use. Xilinx will release future versions to GitHub as well. [ Vitis HLS LLVM GitHub Repository]
Xilinx has partnered with FPGA software company Silexica which has created the SLX Plugin. The plugin extends the Vitis HLS 2020.2 code transformations, leveraging the new injection use model made possible by the open-source project, that can improve HLS latency and throughput.
Based on recent market data, Xilinx is the number one FPGA vendor (by revenue) and therefore its products have a large developer community. As such its Vitis tool chain is used extensively by Xilinx developers. By open sourcing the Vitis HLS Front-end, Xilinx hopes for even wider adoption of the free tool chain.
Xilinx has also engaged multiple universities in HLS customization such as the University of Illinois at Urbana Champaign (UIUC), Imperial College London and Hong Kong University of Science and Technology (HKUST), all who provided supportive quotes in the blog post announcing the program [https://forums.xilinx.com/t5/AI-and-Machine-Learning-Blog/Opening-a-World-of-Possibilities-Vitis-HLS-Front-end-is-Now-Open/ba-p/1211207]. These universities are actively using HLS for advance research. One of the active HKUST projects is particularly interesting. It’s a multi-FPGA HLS that automatically partitions into sub-modules optimized for the application using multiple FPGAs interconnected with network or DDR memory.
Xilinx has been pushing its FPGAs for academic use with its University program [https://www.xilinx.com/support/university.htm]. This is leading to more academic papers that use HLS to program Xilinx FPGAs. The best way to demystify FPGAs is to expose students to the technology early in the careers. The ultimate Xilinx goal is to make FPGAs just another target piece of silicon, like CPUs and GPUs, for programmers.
Vitis HLS Design Flow
The Xilinx Vitis HLS tool chain allows C/C++ code and OpenCL functions that feed a Clang compiler along with HLS-specific pragmas (compiler directives) that eventually are deployed to a FPGA with its logic fabric, RAM blocks, and DSP functions (see figure below). The front end of Vitis is the Clang compiler combined with the HLS LLVM intermediate representation (IR). The HLS LLVM IR layer produces RTL results for spatial hardware deployment. The result of the Vitis HLS Front-end is then fed to a Xilinx FPGA-specific optimization layer and layout back-end that is Xilinx specific and is not part of the open-source code.
I spoke with Nick Ni, director of product marketing for AI and software, Xilinx; DJ Wang, senior director, software engineering, Xilinx; and Frédéric Rivoallon, product manager for Xilinx HLS about the program. They told me that Xilinx wants to engage the software community to develop more libraries for HLS and to scale the ecosystem with more partners. The original pull to open source the Vitis HLS Front-end came the research community that wanted more access to the code to develop new approaches to automated FPGA design.
The move to open source should also stimulate more innovation as advanced users will extend capabilities of HLS. With the accelerated adoption, the HLS tool chain can move beyond FPGAs to other accelerators. It may even be extendable to other FPGA architectures.
Open sourcing the front end can help solve more customer problems. Advanced customers, such as cloud service providers, can deeply customize the FPGA design flow and incorporate it into their preferred programming languages. In addition, with the open sourcing, it will be possible for third parties to add additional languages beyond C/C++ and different LLVM IR; as well as different back-end targets.
Can Xilinx make HLS mainstream?
With all the recent discussions about hardware-software co-design, perhaps HLS is the platform where the two can converge. It is a vehicle for software programmers to get exposed to hardware issues and optimizations, without losing high-level constructs. HLS does require programmers to become more explicit about the target hardware (for example: data paths specifications are required), but that can be used to fine-tune hardware implementations. HLS can be a vehicle for research in this area.
HLS is a different programming paradigm, making it essential that it be taught in universities to reach programmers and engineers early in their careers. Releasing the HLS LLVM IR to open source, there will be the opportunity for greater acceptance and trust in research communities. Xilinx maintains control over HLS for now, as it has been developing it for over 10 years, but over time, the ecosystem will likely play a bigger role in the future of HLS. Xilinx’s vision for HLS is to make it more mainstream, perhaps even as a defacto standard for programming spatial and accelerated computing. Become a real industry standard will take a community of users and active participants from across the ecosystem. Open sourcing HLS should just be the start of this next phase.